Mentor, a Siemens business, today announced that its entire Tessent™ software suite is now certified for Samsung Electronics’ 7nm Low Power Plus (LPP) technology, enabling customers to deploy the industry’s most comprehensive design-for-test (DFT) portfolio on Samsung’s innovative 7nm process technology, which leverages extreme ultraviolet (EUV) lithography.
Built on a foundation of best-in-class solutions for each test discipline, Tessent is a fully integrated test platform sharing a single database and delivering comprehensive silicon test and yield analysis solutions that address the challenges of manufacturing test, debug, and yield ramp for today’s most sophisticated and complex IC designs.
“Mentor’s Tessent products help enable Samsung to meet the biggest challenges that our customers are facing. Tessent TestKompress hierarchical DFT and the Tessent platform provide an efficient plug-and-play method of testing the industry’s largest designs such as for AI devices,” said Jung Yun Choi, vice president of Design Technology Team at Samsung Electronics. “In addition, the in-system test capabilities provide a reliable and proven solution for mission critical products, as well as leading edge markets such as automotive.”
Tessent delivers a powerful test flow that provides total chip coverage for a broad range of markets including ICs for the automotive segment, where quality and reliability are paramount. For example, meeting the stringent ISO 26262 standard for automotive-grade reliability requires that chips support in-system testing during operation to monitor processes and help ensure that the IC is operating free of defects. The Tessent MissionMode Controller supports in-system testing by providing a combination of automation and on-chip IP for enabling semiconductor chips throughout an automotive electronics system to be tested and diagnosed at any point during a vehicle’s functional operation.
“Samsung has a long track record of partnering with market leaders in automotive, AI, and other fast-growing industries where reliability and quality are especially critical,” said Joe Sawicki, executive vice president of IC EDA for Mentor, a Siemens business. “By achieving Samsung 7nm qualification, Mentor’s Tessent DFT platform helps customers take advantage of industry-leading hierarchical DFT and low-impact in-system test functionality. In addition, Tessent Automotive-grade ATPG with cell-aware test further helps Samsung customers to produce the highest quality production test.”
Samsung began wafer production on its highly advanced 7nm LPP processes late last year, offering the world’s leading chip design firms an ideal platform for the production of high performance, low-power and highly area-efficient ICs. Samsung’s 7nm process incorporates EUV technology, which significantly helps reduce the total number of lithographic masks required for each device. This, in turn, helps chipmakers reduce costs and speed time to market.