Siemens Digital Industries Software today announced two breakthrough capabilities for high-level verification of C++ for hardware design: formal property checking and reachability coverage analysis. Designed to be used with Siemens’ Catapult™ software for high-level synthesis and verification, Catapult formal tools uniquely bring known and trusted formal verification methods from the RTL world to high-level design.
Catapult™ Formal Assert software delivers untimed C++ property checking to high-level verification. Designers can now use formal methods to prove that a high-level design representation conforms to a specification. Catapult Formal Assert proves whether a specific property, such as a value range, or specific signal values, can or cannot occur.
Catapult™ Formal CoverCheck is the formal complement to Catapult™ Coverage software, Siemens' simulation-based solution for metrics-driven verification of C++ and SystemC HLS design source. Catapult Formal CoverCheck performs "reachability analysis" on coverage holes and generates a waiver for those items formally proven to be unreachable. Together these two tools help users readily and efficiently achieve coverage closure on their HLS design source.
“Catapult Formal tools are elevating best-in-class verification and design methods into High-Level Design,” said Mo Movahed, vice president and general manager for High-Level Design, Verification and Power, Siemens Digital Industries Software. “By delivering formal methods to C++ verification, we are enabling leading-edge semiconductor teams to take full advantage of High-Level Synthesis and Verification’s power.”
High-level design and synthesis are enjoying increasing adoption across a broad spectrum of applications and markets. Catapult™ HLS software, with its proven ability to deliver material improvements in design productivity and the 100x gain in verification throughput from C++ are leading more and more engineering teams to shift their methodologies.
With this shift, there has been a corresponding desire to bring the known and trusted verification methods that have been refined in RTL design up to High-Level Design. RTL verification has evolved into a metrics-driven methodology where explicit coverage measures must be achieved using a combination of dynamic simulation and formal methods. C++ offers orders of magnitude improvement in simulation throughput, the infrastructure for metrics-driven High-Level Verification is not so well established.
Catapult Formal Assert and CoverCheck, along with Catapult Coverage, help to address this gap. Verification teams now have the same combination of formal methods and coverage analytics to ensure that the C++ representation of the design meets specific targets.
Siemens’ Catapult Formal Assert and CoverCheck is available for early adopters now and will be available to all customers in late 2024. To learn more, visit https://eda.sw.siemens.com/en-US/ic/catapult-high-level-synthesis/hls-verification/formal-verification-tools/
