プレスリリース

Siemens advances integrated circuit test and analysis at 5nm and below

2024年7月9日
Plano, Texas, USA

Siemens Digital Industries Software today introduced Tessent™ Hi-Res Chain software, a new tool designed to address the critical challenges faced by integrated circuit (IC) design and manufacturing teams in advanced technology nodes, where even minor process variations can significantly impact yield and time-to-market. 

As IC designs progress to more advanced nodes at 5nm and below, they become increasingly susceptible to manufacturing variations that can create defects and slow yield ramp. At these geometries, traditional failure analysis (FA) methods can require weeks or months of laboratory effort to investigate. Siemens’ new Tessent Hi-Res Chain tool addresses this problem by rapidly providing transistor-level isolation for scan chain defects. For advanced process nodes where yield ramp heavily relies on chain diagnosis, the new software can boost diagnosis resolution by more than 1.5x, reducing the need for costly extensive failure analysis cycles. 

"Tessent Hi-Res Chain represents a major leap forward in our ability to rapidly identify and address yield-limiting factors in advanced IC designs," said Ankur Gupta, vice president and general manager of the Digital Design Creation Platform division, Siemens Digital Industries Software. "By providing unprecedented accuracy and resolution in defect isolation, we're empowering our customers to accelerate their yield ramp and improve time-to-market for cutting-edge semiconductor products." 

By correlating design information and failure data from manufacturing tests with patterns from Tessent automatic test pattern generation (ATPG), Tessent Hi-Res Chain transforms failing test cycles into actionable insights. The solution employs layout-aware and cell-aware technology to pinpoint a defect's most probable failure mechanism, logic location, and physical location. 

Tessent Hi-Res Chain builds on Siemens' market-leading chain diagnosis capabilities, offering precise defect isolation, even for point defects deep within design control signal networks.  

The new solution maintains Tessent industry-leading accuracy rate, with over 80 percent of its generated reports consistently confirmed through FA processes using Tessent technology. This high level of reliability has made Tessent the go-to solution for yield ramping across multiple technology nodes. 

Tessent Hi-Res Chain is part of Siemens' comprehensive Tessent product family, which offers best-in-class solutions for IC test, functional monitoring, and silicon lifecycle management. These tools work in concert to provide the highest test coverage, accelerate yield ramp, and improve quality and reliability throughout the silicon lifecycle. 

For more information about Tessent Hi-Res Chain and Siemens' full suite of IC design and test solutions, visit www.siemens.com/tessent

シーメンスデジタルインダストリーズソフトウェアは、Siemens Xceleratorビジネス・プラットフォームのソフトウェア、ハードウェア、サービスを最大限に活用し、あらゆる規模の組織がデジタル・トランスフォーメーションを実現する支援をします。シーメンスのソフトウェアと総合的なデジタルツインにより、企業は設計、エンジニアリング、および製造プロセスを最適化し、現在のアイデアを将来の持続可能な製品に転換できるようなります。シーメンスデジタルインダストリーズソフトウェアは、チップからシステム全体、そして製品からプロセスに至るまで、あらゆる産業において変革を加速させます。Siemens Digital Industries Software – Accelerating transformation

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シーメンスデジタルインダストリーズソフトウェア
プレスコミュニケーション Molly Hwa
Email: molly.hwa@siemens.com